Current redundant-execution systems commonly employ a hardware checker circuit that is self-checking. Similar to the hardware checker, in software, is the compare instruction. The compare instruction compares the results from two threads (e.g., store address and data). It may be possible to duplicate the compare instruction in both threads to get the effect of self-checking via duplication.
Unfortunately, by duplicating the compare instruction the architecture would lose the performance advantage of redundant multithreading (RMT). RMT's performance advantage comes from having the leading and trailing threads sufficiently apart such that the leading thread can prefetch cache misses and branch mispredictions for the trailing thread. If the compare instruction is duplicated, not only are additional queues needed, incurring higher overhead, but also the architecture would be unable to keep the two threads sufficiently apart because of the synchronization required in both directions.
The hardware checker instruction ensures a self-checking checker. However, after the check is performed, the processor still needs to ensure that the data just checked reaches protected memory without a fault. Current software does not have visibility into the processor to that level of detail. Thus, without hardware support, the software is not able to ensure that the checked data path proceeds to protected memory without a fault.